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Abstract: A novel polysilicon-assisted silicon-controlled rectifier (SCR) is presented and analyzed in this paper, which is fabricated in HHNEC’s 0.18 μm EEPROM process. The polysilicon-assisted SCRs take advantage of polysilicon layer to help bypass electro-static discharge (ESD) current without occupying extra layout area. TLP current-voltage (I-V) measurement results show that given the same layout areas, robustness performance of polysilicon-assisted SCRs can be improved to 3 times of conventional MLSCR’s. Moreover, one-finger such polysilicon-assisted SCRs, which occupy only 947 μm² layout area, can undergo 7-kV HBM ESD stress. Results further demonstrate that the S-type I-V characteristics of polysilicon-assisted SCRs are adjustable to different operating conditions by changing the device dimensions. Compared with traditional SCRs, this new SCR can bypass more ESD currents and consumes smaller IC area.

[1] Chang, W.J., Ker, M.D., 2007. The impact of drift implant and layout parameters on ESD robustness for on-chip ESD protection devices in 40-V CMOS technology. IEEE Trans. on Device and Materials Reliability, 7(2):324-332.

[2] Ker, M.D., Hsu, S.F., 2006. Component-level measurement for transient-induced latch-up in CMOS ICs under system-level ESD considerations. IEEE Trans. on Device and Materials Reliability, 6(3):461-472.

[3] Lin, C.Y., Ker, M.D., 2007. Low-capacitance SCR with Waffle Layout Structure for On-chip ESD Protection in RF ICs. IEEE Symp. on Radio Frequency Integrated Circuits (RFIC), p.749-752.

[4] Liou, J.J., Salcedo, J.A., Liu, Z.W., 2007. Robust ESD Protection Solutions in CMOS/BiCMOS Technologies. Proc. Int. Workshop on Electron Devices and Semiconductor Technology, p.41-45.

[5] Salcedo, J.A., Liou, J.J., Bernier, J.C., 2005. Design and integration of novel SCR-based devices for ESD protection in CMOS/BiCMOS technologies. IEEE Trans. on Electron Devices, 52(12):2682-2689.

[6] Si Moussa, M., El Kaamouchi, M., Wybo, G., Bens, A., Raskin, J.P., Vanhoenacker-Janvier, D., 2007. Design of a Distributed Amplifier with On-chip ESD Protection Circuit in 130 nm SOI CMOS Technology. Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems, p.111-114.

[7] Tremouilles, D., Bafleur, M., Bertrand, G., Nolhier, N., Mauran, N., Lescouzeres, L., 2004. Latch-up ring design guidelines to improve electrostatic discharge (ESD) protection scheme efficiency. IEEE J. Solid-State Circuits, 39(10):1778-1782.

[8] Wang, A., 2004. A Review of RF ESD Protection Design [RF IC Applications]. IEEE Workshop on Microelectronics and Electron Devices, p.20-23.

[9] Wang, A.Z.H., Feng, H.G., Zhan, R.Y., Xie, H.L., Chen, G., Wu, Q., Guan, X., Wang, Z.H., Zhang, C., 2005. A review on RF ESD protection design. IEEE Trans. on Electron Devices, 52(7):1304-1311.