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Journal of Zhejiang University SCIENCE C 1998 Vol.-1 No.-1 P.

http://doi.org/10.1631/FITEE.2000504


Design and optimization of a gate-controlled dual direction ESD device for an industry-level fluorescent optical fiber temperature sensor


Author(s):  Yang WANG, Xiangliang JIN, Jian YANG, Feng YAN, Yujie LIU, Yan PENG, Jun LUO, Jun YANG

Affiliation(s):  Department of College of Physics and Electronic Science, School of Hunan Normal University, Changsha 410081, China; more

Corresponding email(s):   jinxl@hunnu.edu.cn, pengyan@shu.edu.cn

Key Words:  Electric breakdown, Semiconductor device reliability, CMOS technology


Yang WANG, Xiangliang JIN, Jian YANG, Feng YAN, Yujie LIU, Yan PENG, Jun LUO, Jun YANG. Design and optimization of a gate-controlled dual direction ESD device for an industry-level fluorescent optical fiber temperature sensor[J]. Frontiers of Information Technology & Electronic Engineering, 1998, -1(-1): .

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author="Yang WANG, Xiangliang JIN, Jian YANG, Feng YAN, Yujie LIU, Yan PENG, Jun LUO, Jun YANG",
journal="Frontiers of Information Technology & Electronic Engineering",
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year="1998",
publisher="Zhejiang University Press & Springer",
doi="10.1631/FITEE.2000504"
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%A Yang WANG
%A Xiangliang JIN
%A Jian YANG
%A Feng YAN
%A Yujie LIU
%A Yan PENG
%A Jun LUO
%A Jun YANG
%J Journal of Zhejiang University SCIENCE C
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%I Zhejiang University Press & Springer
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A1 - Yang WANG
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A1 - Feng YAN
A1 - Yujie LIU
A1 - Yan PENG
A1 - Jun LUO
A1 - Jun YANG
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PB - Zhejiang University Press & Springer
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DOI - 10.1631/FITEE.2000504


Abstract: 
The I/O pins of an industry-level fluorescent optical fiber temperature sensors readout circuit need on-chip integrated high-performance electro-static discharge (ESD) protection devices. It is difficult for the failure-level of basic N-type buried layer gate-controlled silicon controlled rectifiers (NBL-GCSCR) manufactured by the 0.18 μm standard BCD process to meet the needs of the above applications. Therefore, an on-chip integrated novel deep N-Well gate-controlled SCR (DNW-GCSCR) with high failure-level is proposed to effectively solve the problems based on the same semiconductor process. TCAD simulation is used to analyze device characteristics. SCRs are tested by transmission line pulses (TLP) to obtain accurate ESD parameters. The holding voltage (24.03 V) of the NBL-GCSCR with longitudinal BJT path is significantly higher than the holding voltage (5.15 V) of the DNW-GCSCR with lateral SCR path of the same size. However, the failure current of the NBL-GCSCR device is 1.71 A, and the failure current of the DNW-GCSCR device is 20.99 A. When the gate size of the DNW-GCSCR is increased from 2 μm to 6 μm, the holding voltage is increased from 3.50 V to 8.38 V. The optimized DNW-GCSCR (6 μm) can be stably applied on target readout circuits for on-chip electrostatic discharge protection.

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