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CLC number: TN432

On-line Access: 2011-07-04

Received: 2010-10-22

Revision Accepted: 2011-01-25

Crosschecked: 2011-05-31

Cited: 3

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Journal of Zhejiang University SCIENCE C 2011 Vol.12 No.7 P.604-607

http://doi.org/10.1631/jzus.C1000372


Design of a novel low power 8-transistor 1-bit full adder cell


Author(s):  Yi Wei, Ji-zhong Shen

Affiliation(s):  Department of Information Science and Electronic Engineering, Zhejiang University, Hangzhou 310027, China

Corresponding email(s):   onlyonewy@126.com, jzshen@zju.edu.cn

Key Words:  Full adder design, Low power, CMOS circuit, Very large-scale integration (VLSI)


Yi Wei, Ji-zhong Shen. Design of a novel low power 8-transistor 1-bit full adder cell[J]. Journal of Zhejiang University Science C, 2011, 12(7): 604-607.

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Abstract: 
An addition is a fundamental arithmetic operation which is used extensively in many very large-scale integration (VLSI) systems such as application-specific digital signal processing (DSP) and microprocessors. An adder determines the overall performance of the circuits in most of those systems. In this paper we propose a novel 1-bit full adder cell which uses only eight transistors. In this design, three multiplexers and one inverter are applied to minimize the transistor count and reduce power consumption. The power dissipation, propagation delay, and power-delay produced using the new design are analyzed and compared with those of other designs using HSPICE simulations. The results show that the proposed adder has both lower power consumption and a lower power-delay product (PDP) value. The low power and low transistor count make the novel 8T full adder cell a candidate for power-efficient applications.

Darkslateblue:Affiliate; Royal Blue:Author; Turquoise:Article

Reference

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[2]Bui, H.T., Wang, Y., Jiang, Y.T., 2002. Design and analysis of low-power 10-transistor full adders using novel XOR-XNOR gates. IEEE Trans. Circ. Syst. II, 49(1):25-30.

[3]Chowdhury, S.R., Banerjee, A., Roy, A., Saha, H., 2008. A high speed 8 transistor full adder design using novel 3 transistor XOR gates. Int. J. Electron. Circ. Syst., 2(4):217-223.

[4]Lee, P.M., Hsu, C.H., Hung, Y.H., 2007. Novel 10-T Full Adders Realized by GDI Structure. Int. Symp. on Integrated Circuits, p.115-118.

[5]Lin, J.F., Hwang, Y.T., Sheu, M.H., Ho, C.C., 2007. A novel high-speed and energy efficient 10-transistor full adder design. IEEE Trans. Circ. Syst. I, 54(5):1050-1059.

[6]Navi, K., Moaiyeri, M.H., Mirzaee, R.F., Hashemipour, O., Nezhad, B.M., 2009. Two new low-power full adders based on majority-not gates. Microelectron. J., 40(1):126-130.

[7]Shalem, R., John, E., John, L.K., 1999. A Novel Low Power Energy Recovery Full Adder Cell. Proc. 9th Great Lakes Symp. on VLSI, p.380-383.

[8]Wang, D., Yang, M.F., Cheng, W., Guan, X.G., Zhu, Z.M., Yang, Y.T., 2009. Novel Low Power Full Adder Cells in 180nm CMOS Technology. 4th IEEE Conf. on Industrial Electronics and Applications, p.430-433.

[9]Xia, B.J., Liu, P., Yao, Q.D., 2009. New method for high performance multiply-accumulator design. J. Zhejiang Univ.-Sci. A, 10(7):1067-1074.

[10]Zhuang, N., Wu, H.M., 1992. A new design of the CMOS full adder. IEEE J. Sol.-State Circ., 27(5):840-844.

[11]Zimmermann, R., Fichtner, W., 1997. Low-power logic styles: CMOS versus pass-transistor logic. IEEE J. Sol.-State Circ., 32(7):1079-1090.

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