Full Text:   <1817>

CLC number: TN702

On-line Access: 2012-12-09

Received: 2012-07-06

Revision Accepted: 2012-09-29

Crosschecked: 2012-11-12

Cited: 1

Clicked: 3360

Citations:  Bibtex RefMan EndNote GB/T7714

-   Go to

Article info.
1. Reference List
Open peer comments

Journal of Zhejiang University SCIENCE C 2012 Vol.13 No.12 P.944-950


A novel ternary JK flip-flop using the resonant tunneling diode literal circuit

Author(s):  Mi Lin, Ling-ling Sun

Affiliation(s):  School of Electronics and Information, Hangzhou Dianzi University, Hangzhou 310018, China

Corresponding email(s):   linmi@hdu.edu.cn

Key Words:  Resonant tunneling diode (RTD), Ternary logic, Literal circuit, Module-3 operation, JK flip-flop

Share this article to: More <<< Previous Article|

Mi Lin, Ling-ling Sun. A novel ternary JK flip-flop using the resonant tunneling diode literal circuit[J]. Journal of Zhejiang University Science C, 2012, 13(12): 944-950.

@article{title="A novel ternary JK flip-flop using the resonant tunneling diode literal circuit",
author="Mi Lin, Ling-ling Sun",
journal="Journal of Zhejiang University Science C",
publisher="Zhejiang University Press & Springer",

%0 Journal Article
%T A novel ternary JK flip-flop using the resonant tunneling diode literal circuit
%A Mi Lin
%A Ling-ling Sun
%J Journal of Zhejiang University SCIENCE C
%V 13
%N 12
%P 944-950
%@ 1869-1951
%D 2012
%I Zhejiang University Press & Springer
%DOI 10.1631/jzus.C1200214

T1 - A novel ternary JK flip-flop using the resonant tunneling diode literal circuit
A1 - Mi Lin
A1 - Ling-ling Sun
J0 - Journal of Zhejiang University Science C
VL - 13
IS - 12
SP - 944
EP - 950
%@ 1869-1951
Y1 - 2012
PB - Zhejiang University Press & Springer
ER -
DOI - 10.1631/jzus.C1200214

A literal circuit with a three-track-output structure is presented based on resonant tunneling diodes (RTDs). It can be transformed conveniently into a single-track-output structure according to the definition and properties of the literal operation. A ternary resonant tunneling JK flip-flop is created based on the RTD literal circuit and the module-3 operation, and the JK flip-flop also has two optional types of output structure. The design of the ternary RTD JK flip-flop is verified by simulation. The RTD literal circuit is the key design component for achieving various types of multi-valued logic (MVL) flip-flops. It can be converted into ternary D and JK flip-flops, and the ternary JK flip-flop can also be converted simply and conveniently into ternary D and ternary T flip-flops when the input signals satisfy certain logical relationships. All these types of flip-flops can be realized using the traditional Karnaugh maps combined with the literal and module-3 operations. This approach offers a novel design method for MVL resonant tunneling flip-flop circuits.

Darkslateblue:Affiliate; Royal Blue:Author; Turquoise:Article


[1]Berezowski, K.S., Vrudhula, S.B.K., 2005. Automatic Design of Binary and Multiple-Valued Logic Gates on RTD Series. 8th Euromicro Conf. on Digital System Design— Architectures, Methods and Tools, p.139-142.

[2]Berezowski, K.S., Vrudhula, S.B.K., 2007. Multiple-Valued Logic Circuits Design Using Negative Differential Resistance Devices. Proc. 37th Int. Symp. on Multiple-Valued Logic, p.24-30.

[3]Bhattacharya, M., Kulkarni, S., Gonzalez, A., Mazumder, P., 2000. Prototyping Technique for Large-Scale RTD-CMOS Circuits. IEEE Int. Symp. on Circuits and Systems, p.635-638.

[4]Ebata, T., Omae, U., Machida, K., Hoshi, K., Waho, T., 2010. Enhancement of Comparator Operation Speed by Using Negative-Differential-Resistance Devices. Proc. IEEE Int. Symp. on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems, p.3020-3023.

[5]González, A.F., Bhattacharya, M., Kulkarni, S., Mazumder, P., 2001. CMOS implementation of a multiple-valued logic signed-digit full adder based on negative-differential-resistance devices. IEEE J. Sol. State Circ., 36(6):924-932.

[6]Guo, W.L., 2009. Resonant Tunneling Devices and Their Applications. Science Press, Beijing, China, p.1-46, 232-234, 350-353 (in Chinese).

[7]Hang, G.Q., Zhou, X.C., 2011. Novel CMOS Ternary Flip-Flops Using Double Pass-Transistor Logic. Int. Conf. on Electric Information and Control Engineering, p.5978-5981.

[8]Homma, N., Saito, K., Aoki, T., 2012. Formal Design of Multiple-Valued Arithmetic Algorithms over Galois Fields and Its Application to Cryptographic Processor. Proc. IEEE 42nd Int. Symp. on Multiple-Valued Logic, p.110-115.

[9]Lee, J., Choi, S., Yang, K., 2010. Implementation of a 4:1 Multiplexing Quantum-Effect IC Based on RTD Circuit Topology. 10th IEEE Conf. on Nanotechnology, p.211-213.

[10]Li, X.B., 2009. Digital monolithic integrated circuits based on RTTs. Micronanoelectr. Technol., 46(1):1-9 (in Chinese).

[11]Liang, D.S., Gan, K.J., Chun, K.Y., 2010. Frequency Divider Design Using the Λ-Type Negative-Differential-Resistance Circuit. Proc. 53rd IEEE Int. Midwest Symp. on Circuits and Systems, p.969-972.

[12]Lin, M., Sun, Z.Y., Shen, J.Z., 2004. Design of NAND and NOR logic gates based on RTD. Bull. Sci. Technol., 20(5):434-437 (in Chinese).

[13]Lin, M., Lü, W.F., Sun, L.L., 2007. Design of ternary NAND and NOR gates based on resonant tunneling devices. J. Semicond., 28(12):1983-1987 (in Chinese).

[14]Lin, M., Lü, W.F., Sun, L.L., 2011a. Design of ternary D flip-flop with pre-set and pre-reset functions based on resonant tunneling diode literal circuit. J. Zhejiang Univ.-Sci. C (Comput. & Electron.), 12(6):507-514.

[15]Lin, M., Zhang, H.P., Sun, L.L., 2011b. Testability Design of Multi-valued RTD Circuits. Int. Conf. on Electronics, Communications and Control, p.510-513.

[16]Núñez, J., Quintana, J.M., Avedillo, M.J., 2007. Correct DC Operation in RTD-Based Ternary Inverters. Proc. 2nd IEEE Int. Conf. on Nano/Micro Engineered and Molecular Systems, p.860-865.

[17]Núñez, J., Quintana, J.M., Avedillo, M.J., 2008. Design of RTD-Based NMIN/NMAX Gates. 8th IEEE Conf. on Nanotechnology, p.518-521.

[18]Sasao, T., 2012. Multiple-Valued Input Index Generation Functions: Optimization by Linear Transformation. Proc. IEEE 42nd Int. Symp. on Multiple-Valued Logic, p.185-190.

[19]Suzuki, S., Hinata, K., Shiraishi, M., Asada, M., Sugiyama, H., Yokoyama, H., 2010. RTD Oscillators at 430–460 GHz with High Output Power (~200 μW) Using Integrated Offset Slot Antennas. Int. Conf. on Indium Phosphide and Related Materials, p.152-155.

[20]Uemura, T., Baba, T., 2000. Demonstration of a Novel Multiple-Valued T-Gate Using Multiple-Junction Surface Tunnel Transistors and Its Application to Three-Valued Data Flip-Flop. Proc. 30th IEEE Int. Symp. on Multiple-Valued Logic, p.305-310.

[21]Wu, H.X., Zhong, S.N., Cai, Q.L., Xia, Q.B., Chen, Y.Y., 2012. Design of quaternary logic circuits based on multiple-valued current mode. Lect. Notes Electr. Eng., 138:479-488.

[22]Wu, X.W., 1994. The Design Theory of Multiple Logic Circuits. Hangzhou University Press, Hangzhou, China, p.18-43, 233-261 (in Chinese).

[23]Wu, X.W., Bi, D.X., 1984. Research of the ternary flip-flop based on the module algebra. Acta Electron. Sin., 12(3):6-13 (in Chinese).

[24]Yuminaka, Y., Okui, M., 2012. Efficient Data Transmission Using Multiple-Valued Pulse-Position Modulation. Proc. IEEE 42nd Int. Symp. on Multiple-Valued Logic, p.7-12.

[25]Zhang, W.C., Wu, N.J., 2008. Compact voltage-mode multi-valued literal gate using nanoscale ballistic MOSFETs. Electron. Lett., 44(16):968-969.

Open peer comments: Debate/Discuss/Question/Opinion


Please provide your name, email address and a comment

Journal of Zhejiang University-SCIENCE, 38 Zheda Road, Hangzhou 310027, China
Tel: +86-571-87952783; E-mail: cjzhang@zju.edu.cn
Copyright © 2000 - Journal of Zhejiang University-SCIENCE