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CLC number: TN918

On-line Access: 2020-04-21

Received: 2018-10-29

Revision Accepted: 2019-05-09

Crosschecked: 2020-03-06

Cited: 0

Clicked: 1027

Citations:  Bibtex RefMan EndNote GB/T7714

 ORCID:

Vijay Dahiphale

https://orcid.org/0000-0002-7113-3666

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Frontiers of Information Technology & Electronic Engineering  2020 Vol.21 No.4 P.615-628

http://doi.org/10.1631/FITEE.1800681


Design and implementation of various datapath architectures for the ANU lightweight cipher on an FPGA


Author(s):  Vijay Dahiphale, Gaurav Bansod, Ankur Zambare, Narayan Pisharoty

Affiliation(s):  Pune Institute of Computer Technology, Pune 411043, India; more

Corresponding email(s):   vijaydahiphale96@gmail.com, gaurav249@gmail.com

Key Words:  Lightweight cryptography, Internet of Things (IoT), Embedded security, Encryption, FPGA, Datapath design


Vijay Dahiphale, Gaurav Bansod, Ankur Zambare, Narayan Pisharoty. Design and implementation of various datapath architectures for the ANU lightweight cipher on an FPGA[J]. Frontiers of Information Technology & Electronic Engineering, 2020, 21(4): 615-628.

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Abstract: 
Since the dawn of the Internet of Things (IoT), data and system security has been the major concern for developers. Because most IoT devices operate on 8-bit controllers with limited storage and computation power, encryption and decryption need to be implemented at the transmitting and receiving ends, respectively, using lightweight ciphers. We present novel architectures for hardware implementation for the ANU cipher and present results associated with each architecture. The ANU cipher is implemented at 4-, 8-, 16-, and 32-bit datapath sizes on four different field-programmable gate array (FPGA) platforms under the same implementation condition, and the results are compared on every performance metric. Unlike previous ANU architectures, the new architectures have parallel substitution boxes (S-boxes) for high throughput and hardware optimization. With these different datapath designs, ANU cipher proves to be the obvious choice for implementing security in extremely resource-constrained systems.

基于现场可编程门阵列的不同数据路径架构ANU轻量级密码的设计与实现


Vijay DAHIPHALE1, Gaurav BANSOD1, Ankur ZAMBARE1, NarayanPISHAROTY2
1浦那计算机技术学院,印度浦那,411043
2Iziel医疗私人有限公司,印度浦那,411028

摘要:自物联网(IoT)诞生以来,数据与系统安全一直是开发者关注的重点。由于大多数物联网设备在8位控制器上运行,其容量和计算力有限,因此需要使用轻量级密码在发送端和接收端分别进行加密和解密。提出用于ANU密码硬件实现的新架构,并给出每一架构的相关结果。在相同实施条件下,在4种不同现场可编程门阵列(FPGA)上分别以4位、8位、16位和32位的数据路径尺寸实现ANU密码,并比较每一性能指标。与以往ANU密码架构不同,新架构具有用于高吞吐量和硬件优化的并行替换盒(S盒)。通过不同数据路径设计,在资源极其有限的系统中,ANU密码被证明是实现安全性的最佳选择。

关键词:轻量级密码;物联网(IoT);嵌入式系统安全;加密;现场可编程门阵列;数据路径设计

Darkslateblue:Affiliate; Royal Blue:Author; Turquoise:Article

Reference

[1]Anandakumar NN, Peyrin T, Poschmann A, 2014. A very compact FPGA implementation of LED and PHOTON. Int Conf on Cryptology in India, p.304-321.

[2]Aysu A, Gulcan E, Schaumont P, 2014. SIMON says, break the area records for symmetric key block ciphers on FPGAs. http://eprint.iacr.org/2014/237

[3]Bansod G, Patil A, Sutar S, et al., 2016a. ANU: an ultra lightweight cipher design for security in IoT. Secur Commun Netw, 9(18):5238-5251.

[4]Bansod G, Patil A, Sutar S, et al., 2016b. An ultra lightweight encryption design for security in pervasive computing. 2nd Int Conf on Big Data Security on Cloud, p.79-84.

[5]Bogdanov A, Knudsen LR, Leander G, et al., 2007. PRESENT: an ultra-lightweight block cipher. Int Workshop on Cryptographic Hardware and Embedded Systems, p.450- 466.

[6]Bulens P, Standaert FX, Quisquater JJ, et al., 2008. Implementation of the AES-128 on Virtex-5 FPGAs. Int Conf on Cryptology in Africa, p.16-26.

[7]Chu JF, Benaissa M, 2012. Low area memory-free FPGA implementation of the AES algorithm. 22nd Int Conf on Field Programmable Logic and Applications, p.623-626.

[8]Dahiphale V, Raut H, Bansod G, 2019a. Design and implementation of novel datapath designs of lightweight cipher rectangle for resource constrained environment. Multimed Tools and Appl, 78:23659-23688.

[9]Dahiphale V, Bansod G, Zambare A, 2019b. Lightweight datapath implementation of ANU cipher for resource- constrained environments. Intelligent Computing, p.834- 846.

[10]Guo X, Chen Z, Schaumont P, 2008. Energy and performance evaluation of an FPGA-based SoC platform with AES and PRESENT coprocessors. Int Workshop on Embedded Computer Systems, p.106-115.

[11]Hanley N, O’Neill M, 2012. Hardware comparison of the ISO/IEC 29192-2 block ciphers. IEEE Computer Society Annual Symp on VLSI, p.57-62.

[12]Kaps JP, 2008. Chai-Tea, Cryptographic Hardware Implementations of xTEA. Int Conf on Cryptology in India, p.363-375.

[13]Kaps JP, Sunar B, 2006. Energy comparison of AES and SHA-1 for ubiquitous computing. Int Conf on Embedded and Ubiquitous Computing, p.372-381.

[14]Lara-Nino CA, Diaz-Perez A, Morales-Sandoval M, 2017. Lightweight hardware architectures for the PRESENT cipher in FPGA. IEEE Trans Circ Syst, 64(9):2544- 2555.

[15]Mace F, Standaert FX, Quisquater JJ, 2007. FPGA implementation(s) of a scalable encryption algorithm. IEEE Trans Very Large Scale Integr Syst, 16(2):212-216.

[16]National Institute of Standards and Technology, 1999. Data Encryption Standard (DES). Federal Information Processing Standards. http://csrc.nist.gov/publications/fips/ fips46-3/fips46-3.pdf

[17]National Institute of Standards and Technology, 2001. Advanced Encryption Standard (AES). Federal Information Processing Standards. http://csrc.nist.gov/publications/fips/fips197/fips-197.pdf

[18]Okabe T, 2017. FPGA implementation and evaluation of lightweight block cipher-BORON. Int J Eng Dev Res, 3(4):2321-9939.

[19]Poschmann A, 2009. Lightweight Cryptography— Cryptographic Engineering for a Pervasive World. PhD Thesis, Europaeischer University, Germany.

[20]Standaert FX, Piret G, Rouvroy G, et al., 2007. FPGA implementations of the ICEBERG block cipher. Integration, 40(1):20-27.

[21]Xilinx, 2018a. Spartan-3A FPGA Family: Data Sheet. http://www.xilinx.com/support/documentation/data_sheets/ds529.pdf [Accessed on Dec. 18, 2018].

[22]Xilinx, 2018b. Spartan-6 FPGA Configuration. http://www.xilinx.com/support/documentation/user_guides/ug380.pdf [Accessed on Mar. 22, 2018].

[23]Xu T, Wendt JB, Potkonjak M, 2014. Security of IoT systems: design challenges and opportunities. IEEE/ACM Int Conf on Computer-Aided Design, p.417-423.

[24]Yalla P, Kaps JP, 2009. Lightweight cryptography for FPGAs. Int Conf on Reconfigurable Computing and FPGAs, p.225-230.

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