CLC number: TN918
On-line Access: 2024-08-27
Received: 2023-10-17
Revision Accepted: 2024-05-08
Crosschecked: 2020-03-06
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Vijay Dahiphale, Gaurav Bansod, Ankur Zambare, Narayan Pisharoty. Design and implementation of various datapath architectures for the ANU lightweight cipher on an FPGA[J]. Frontiers of Information Technology & Electronic Engineering, 2020, 21(4): 615-628.
@article{title="Design and implementation of various datapath architectures for the ANU lightweight cipher on an FPGA",
author="Vijay Dahiphale, Gaurav Bansod, Ankur Zambare, Narayan Pisharoty",
journal="Frontiers of Information Technology & Electronic Engineering",
volume="21",
number="4",
pages="615-628",
year="2020",
publisher="Zhejiang University Press & Springer",
doi="10.1631/FITEE.1800681"
}
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%T Design and implementation of various datapath architectures for the ANU lightweight cipher on an FPGA
%A Vijay Dahiphale
%A Gaurav Bansod
%A Ankur Zambare
%A Narayan Pisharoty
%J Frontiers of Information Technology & Electronic Engineering
%V 21
%N 4
%P 615-628
%@ 2095-9184
%D 2020
%I Zhejiang University Press & Springer
%DOI 10.1631/FITEE.1800681
TY - JOUR
T1 - Design and implementation of various datapath architectures for the ANU lightweight cipher on an FPGA
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A1 - Gaurav Bansod
A1 - Ankur Zambare
A1 - Narayan Pisharoty
J0 - Frontiers of Information Technology & Electronic Engineering
VL - 21
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%@ 2095-9184
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PB - Zhejiang University Press & Springer
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DOI - 10.1631/FITEE.1800681
Abstract: Since the dawn of the Internet of Things (IoT), data and system security has been the major concern for developers. Because most IoT devices operate on 8-bit controllers with limited storage and computation power, encryption and decryption need to be implemented at the transmitting and receiving ends, respectively, using lightweight ciphers. We present novel architectures for hardware implementation for the ANU cipher and present results associated with each architecture. The ANU cipher is implemented at 4-, 8-, 16-, and 32-bit datapath sizes on four different field-programmable gate array (FPGA) platforms under the same implementation condition, and the results are compared on every performance metric. Unlike previous ANU architectures, the new architectures have parallel substitution boxes (S-boxes) for high throughput and hardware optimization. With these different datapath designs, ANU cipher proves to be the obvious choice for implementing security in extremely resource-constrained systems.
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