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Journal of Zhejiang University SCIENCE A 2008 Vol.9 No.4 P.510~516

10.1631/jzus.A071449


A semi-custom design methodology for design performance optimization


Author(s):  Dong-ming LV, Pei-yong ZHANG, Dan-dan ZHENG, Xiao-lang YAN, Bo ZHANG, Li QUAN

Affiliation(s):  Institute of VLSI Design, Zhejiang University, Hangzhou 310027, China

Corresponding email(s):   lvdm@vlsi.zju.edu.cn, zhangpy@vlsi.zju.edu.cn

Key Words:  Transistor tuning, Cross-talk, Circuit decomposing


Dong-ming LV, Pei-yong ZHANG, Dan-dan ZHENG, Xiao-lang YAN, Bo ZHANG, Li QUAN. A semi-custom design methodology for design performance optimization[J]. Journal of Zhejiang University Science A, 2008, 9(4): 510~516.

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author="Dong-ming LV, Pei-yong ZHANG, Dan-dan ZHENG, Xiao-lang YAN, Bo ZHANG, Li QUAN",
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doi="10.1631/jzus.A071449"
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J0 - Journal of Zhejiang University Science A
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Abstract: 
We present a semi-custom design methodology based on transistor tuning to optimize the design performance. Compared with other transistor tuning approaches, our tuning process takes the cross-talk effect into account and prominently reduces the complexity for circuit simulation and analysis by decomposing the circuit network utilizing graph theory. Furthermore, the incremental placement and routing for the corresponding transistor tuning in conventional approaches is not required in our methodology, which might induce timing graph variation and additional iterations for design convergence. This methodology combines the flexible automated circuit tuning and physical design tools to provide more opportunities for design optimization throughout the design cycle.

Darkslateblue:Affiliate; Royal Blue:Author; Turquoise:Article

Reference

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[3] Fishburn, J.P., Dunlop, A.E., 1985. TILOS: A Posynomial Programming Approach to Transistor Sizing. Proc. Int. Conf. on Computer-Aided Design, p.326-328.

[4] Kabbani, A., Al-Khalili, D., Al-Khalili, A.J., 2005. Logical Path Delay Distribution and Transistor Sizing. Proc. Int. IEEE North-East Workshop on Circuits and Systems Conf., p.391-394.

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[7] Lu, P.F., Northrop, G.A., Chiarot, K., 2005. A Semi-Custom Design of Branch Address Calculator in the IBM Power4 Microprocessor. IEEE VLSI-TSA Int. Symp., p.329-332.

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[9] Santos, C., Ferrao, D., Lazzari, C., Wilke, G., Guntzel, J.L., Reis, R., 2005a. Effects of Using a Pin-to-Pin Delay Model on a Library-Free Transistor/Gate Sizing Scheme. Proc. 48th Midwest Symp. on Circuits and Systems, p.315-318.

[10] Santos, C., Ferrao, D., Reis, R., Guntzel, J.L., 2005b. Incremental Timing Optimization for Automatic Layout Generation. IEEE Int. Symp. on Circuit and Systems, p.3567-3570.

[11] Talukdar, D., Sridhar, R., 1996. An Analytical Approach to Fine Tuning in CMOS Wave-Pipelining. Proc. Int. Application Specific Integrated Circuits Conf., p.205-208.

[12] Vittal, A., Chen, L.H., Marek-Sadowska, M., Wang, K.P., Yang, S., 1999. Modeling Crosstalk in Resistive VLSI InterConnections. Int. Conf. on VLSI Design, p.470-475.

[13] Yelamarthi, K., Chen, C.I.H., 2007. Transistor Sizing for Load Balance of Multiple Paths in Dynamic CMOS for Timing Optimization. 8th Int. Symp. on Quality Electronic Design, p.426-431.

[14] Yu, X.Y., Oklobdzija, V.G., Walker, W.W., 2003. An Efficient Transistor Optimizer for Custom Circuits. Proc. Int. Symp. on Circuits and Systems, p.197-200.

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