CLC number: TN402
On-line Access: 2024-08-27
Received: 2023-10-17
Revision Accepted: 2024-05-08
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Dong-ming LV, Pei-yong ZHANG, Dan-dan ZHENG, Xiao-lang YAN, Bo ZHANG, Li QUAN. A semi-custom design methodology for design performance optimization[J]. Journal of Zhejiang University Science A, 2008, 9(4): 510-516.
@article{title="A semi-custom design methodology for design performance optimization",
author="Dong-ming LV, Pei-yong ZHANG, Dan-dan ZHENG, Xiao-lang YAN, Bo ZHANG, Li QUAN",
journal="Journal of Zhejiang University Science A",
volume="9",
number="4",
pages="510-516",
year="2008",
publisher="Zhejiang University Press & Springer",
doi="10.1631/jzus.A071449"
}
%0 Journal Article
%T A semi-custom design methodology for design performance optimization
%A Dong-ming LV
%A Pei-yong ZHANG
%A Dan-dan ZHENG
%A Xiao-lang YAN
%A Bo ZHANG
%A Li QUAN
%J Journal of Zhejiang University SCIENCE A
%V 9
%N 4
%P 510-516
%@ 1673-565X
%D 2008
%I Zhejiang University Press & Springer
%DOI 10.1631/jzus.A071449
TY - JOUR
T1 - A semi-custom design methodology for design performance optimization
A1 - Dong-ming LV
A1 - Pei-yong ZHANG
A1 - Dan-dan ZHENG
A1 - Xiao-lang YAN
A1 - Bo ZHANG
A1 - Li QUAN
J0 - Journal of Zhejiang University Science A
VL - 9
IS - 4
SP - 510
EP - 516
%@ 1673-565X
Y1 - 2008
PB - Zhejiang University Press & Springer
ER -
DOI - 10.1631/jzus.A071449
Abstract: We present a semi-custom design methodology based on transistor tuning to optimize the design performance. Compared with other transistor tuning approaches, our tuning process takes the cross-talk effect into account and prominently reduces the complexity for circuit simulation and analysis by decomposing the circuit network utilizing graph theory. Furthermore, the incremental placement and routing for the corresponding transistor tuning in conventional approaches is not required in our methodology, which might induce timing graph variation and additional iterations for design convergence. This methodology combines the flexible automated circuit tuning and physical design tools to provide more opportunities for design optimization throughout the design cycle.
[1] Chen, R.Y., Yip, P., Konstadinidis, G., Demas, A., Klass, F., Mains, R., Schmitt, M., Bistry, D., 2002. Timing Window Applications in UltraSPARC-IIIiTM Microprocessor Design. Proc. IEEE Int. Conf. on Computer Design: VLSI in Computers and Processors, p.158-163.
[2] Cormen, T.H., Leiserson, C.E., Rivest, R.L., 1990. Introduction to Algorithms. MIT Press, USA, p.641-732.
[3] Fishburn, J.P., Dunlop, A.E., 1985. TILOS: A Posynomial Programming Approach to Transistor Sizing. Proc. Int. Conf. on Computer-Aided Design, p.326-328.
[4] Kabbani, A., Al-Khalili, D., Al-Khalili, A.J., 2005. Logical Path Delay Distribution and Transistor Sizing. Proc. Int. IEEE North-East Workshop on Circuits and Systems Conf., p.391-394.
[5] Kao, W.H., Fathi, N., Lee, C.H., 1985. Algorithms for Automatic Transistor Sizing in CMOS Digital Circuits. Proc. ACM/IEEE Conf. on Design Automation, p.781-784.
[6] Ketkar, M., Kasamsetty, K., Sapatnekar, S., 2000. Convex Delay Models for Transistor Sizing. Proc. Design Automation Conf., p.655-660.
[7] Lu, P.F., Northrop, G.A., Chiarot, K., 2005. A Semi-Custom Design of Branch Address Calculator in the IBM Power4 Microprocessor. IEEE VLSI-TSA Int. Symp., p.329-332.
[8] Northrop, G.A., Lu, P.F., 2001. A Semi-Custom Design Flow in High-Performance Microprocessor Design. Proc. Design Automation Conf., p.426-431.
[9] Santos, C., Ferrao, D., Lazzari, C., Wilke, G., Guntzel, J.L., Reis, R., 2005a. Effects of Using a Pin-to-Pin Delay Model on a Library-Free Transistor/Gate Sizing Scheme. Proc. 48th Midwest Symp. on Circuits and Systems, p.315-318.
[10] Santos, C., Ferrao, D., Reis, R., Guntzel, J.L., 2005b. Incremental Timing Optimization for Automatic Layout Generation. IEEE Int. Symp. on Circuit and Systems, p.3567-3570.
[11] Talukdar, D., Sridhar, R., 1996. An Analytical Approach to Fine Tuning in CMOS Wave-Pipelining. Proc. Int. Application Specific Integrated Circuits Conf., p.205-208.
[12] Vittal, A., Chen, L.H., Marek-Sadowska, M., Wang, K.P., Yang, S., 1999. Modeling Crosstalk in Resistive VLSI InterConnections. Int. Conf. on VLSI Design, p.470-475.
[13] Yelamarthi, K., Chen, C.I.H., 2007. Transistor Sizing for Load Balance of Multiple Paths in Dynamic CMOS for Timing Optimization. 8th Int. Symp. on Quality Electronic Design, p.426-431.
[14] Yu, X.Y., Oklobdzija, V.G., Walker, W.W., 2003. An Efficient Transistor Optimizer for Custom Circuits. Proc. Int. Symp. on Circuits and Systems, p.197-200.
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